Adaptive programming for flash memories

ABSTRACT

A method to adjust the programming voltage in flash memory when the programming time exceeds specification. A method to adjust the programming voltage of flash memory after a predetermined number of erase/write cycles.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional U.S. application Ser. No. 12/973,250,filed Dec. 20, 2010, the content of which is hereby incorporated byreference.

BACKGROUND

This invention relates to the field of integrated circuits. Moreparticularly, this invention relates to erasing and writing to flashmemories.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a flash integrated circuit.

FIGS. 2A and 2B are cross-sections of an NMOS flash bit during an eraseand a write operation.

FIG. 3 (Prior Art) is a graph of cumulative erase time.

FIGS. 4A and 4B (Prior Art) are graphs of cumulative erase timedistributions for flash memory blocks from two different flashintegrated circuits.

FIGS. 5A and 5B are graphs of the cumulative erase time distributionsusing an adaptive erase voltage according to an embodiment.

FIGS. 6A, 6B, and 6C illustrate the tightening of an erase timedistribution according to an embodiment.

FIGS. 7A and 7B illustrate the tightening of an erase time distributionaccording to another embodiment.

FIG. 8 is a flow diagram describing an embodiment for adaptiveprogramming over the lifetime of a flash circuit.

FIGS. 9A, 9B, and 9C are plots of the erase time after various numbersof erase cycles for flash memory according to an embodiment.

FIG. 10 is a flow diagram describing another embodiment for adaptiveprogramming over the lifetime of a flash circuit.

FIGS. 11A and 11B are cross-sections of a PMOS flash bit during an eraseand a write operation.

DETAILED DESCRIPTION

The example embodiments are described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the exampleembodiments. Several aspects are described below with reference toexample applications for illustration. It should be understood thatnumerous specific details, relationships, and methods are set forth toprovide a full understanding of the example embodiments. One skilled inthe relevant art, however, will readily recognize that the exampleembodiments can be practiced without one or more of the specific detailsor with other methods. In other instances, well-known structures oroperations are not shown in detail to avoid obscuring the embodiment.The example embodiments are not limited by the illustrated ordering ofacts or events, as some acts may occur in different orders and/orconcurrently with other acts or events. Furthermore, not all illustratedacts or events are required to implement a methodology in accordancewith the example embodiments.

The term “verify” refers to the process of reading a flash bit todetermine if a write or erase has been successful.

The term “adaptive programming voltage” is an adaptive erase voltage oran adaptive write voltage that may be selected in order to erase orwrite a portion of a flash memory within a specified time period. Theadaptive programming voltage may be applied to the control gate or maybe applied to an electrically isolated well (flash well) under the flashbit. Adaptive erase voltages or adaptive write voltages may besimultaneously applied to the control gate and the flash well to eraseor write the flash bit within a specified time.

The term “programming” refers to the operation of writing data to thefloating gate or erasing data from the floating gate. During aprogramming operation, electrons may be trapped on the floating gate ormay be removed from the floating gate.

A flash integrated circuit 100 containing a flash memory 106 is shown inFIG. 1. Also included in the integrated circuit are a central processorunit (“CPU”) 102 and an Application Programmer Interface (“API”) 104.The integrated circuit may also contain other circuits such as a StaticRandom Access (“SRAM”) memory, a phase locked loop, and analog circuitry(that are not shown to simplify the drawing).

The API 104 contains the software program that controls the flash read,write, and erase functions. When the CPU 102 wants to access the flashmemory 106 it may send a request containing the targeted data address tothe API 104. The API 104 then sends the proper signals to the bitlines,wordlines, and sense amps in the flash memory 106 to perform therequested memory access operation. For example, when the CPU 102 wantsto write data into flash memory 106, it sends this request to the API104. The API 1004 then sends the proper signals to the specified memoryblock 108 to erase the block and then rewrite the new data into thememory block 108. The memory blocks 108 typically contain 1 to 8 megabit(“M”) flash bits. Memory sectors 110 within the memory block 108typically contain 64K to 1M flash bits. During a data write, the fullflash memory 106 may be erased and rewritten, a memory block 108 may beerased and rewritten, or a memory sector 110 may be erased andrewritten—depending upon the flash architecture. In the example below ablock erase and write will be used to illustrate the embodiment.

FIG. 2A shows an example of an NMOS flash bit 2000 during an erase usingFowler-Nordheim (“FN”) tunneling. The NMOS flash bit is fabricated in anisolated pwell 2002 and it includes a gate dielectric 2006 (usuallycomposed of oxide), a floating gate 2008 (usually composed ofpolysilicon), an interpoly dielectric 2010 (usually composed ofoxide/nitride/oxide layers), a control gate 2012 (usually composed ofpoly silicon but may also be FUSI or a metal gate), and an N+ source anddrain, 2004 and 2016. During erase, a negative voltage 2014 is appliedto the control gate 2012 and a positive voltage 2016 is applied to theisolated pwell 2002. This causes electrons 2020 to tunnel through thegate dielectric 2006 from the floating gate 2008 to the isolated pwellsubstrate 2002. A control gate voltage 2014 of about −8.5V and anisolated pwell voltage 2016 of about +8.5V is used in the exampleembodiment for illustrative purposes. Actual voltages may differsomewhat depending upon structural details of the flash bit 2000. Inaddition, the source and drain, 2004 and 2016, are floated in theexample embodiment. Although this NMOS flash bit is shown to be in anisolated p-well, the flash bit may be alternatively constructed in ap-substrate (without an isolated pwell). With this alternativestructure, the control gate voltage 2014 may be raised to −14 volts ormore and the substrate voltage may be ground.

FIG. 2B shows an example of a NMOS flash bit 2100 during a write usingFN tunneling. During write, a positive voltage 2114 is applied to thecontrol gate 2112 and the isolated pwell 2102 is grounded 2116. Thiscauses electrons to tunnel 2120 through the gate dielectric 2106 fromthe isolated pwell substrate 2102 to the floating gate 2108. A controlgate voltage 2114 of about 17V and an isolated pwell voltage 2116 of 0Vare used in the example embodiment for illustrative purposes. Actualvoltages may differ somewhat from these levels, depending upon thestructural details of the NMOS flash bit 2100.

FIG. 3 shows an example plot 3000 of cumulative erase time vs. erasevoltage. A series of erase voltage pulses of approximately 10millisecond duration—each followed by a verify operation—is repeateduntil all of the flash bits in a flash block pass the specified erasedbit turn on voltage (“Vt”). For example, a first erase period extendsuntil time t1 3002 where an erase verify operation is performed. If theflash block fails the erased Vt specification then a second series oferase voltage pulses is applied to the flash block until time t2 3004where an erase verify is again performed. This procedure is repeateduntil either the flash block passes the erase Vt specification or amaximum number of allowed erase verify steps are reached.

FIG. 4A shows a plot of the number of blocks that erase by a given erasetime versus the cumulative erase time for a flash integrated circuitwith fast erase flash bits. The majority of the blocks erase in lessthan 1 second and virtually all the blocks are erased in less than 2seconds.

FIG. 4B shows a plot of the number of blocks that erase by a given erasetime versus the cumulative erase time for a flash integrated circuitwith slower to erase flash bits. The majority of blocks take longer than1 second to erase. If the erase time specification is less than 3seconds, any die with chips containing memory blocks that take longerthan 3 seconds to erase are scrapped. Flash bits that take a long timeto erase may significantly extend the endurance testing time becauseflash memories may be erased and rewritten over 10,000 times.

FIGS. 5A and 5B show the block erase times for the memory blocks whosedistributions are shown in FIGS. 4A and 4B using the adaptive erasemethod according to an embodiment infra. The block erase times of bothdistributions are reduced to approximately less than one second.

NMOS flash bits may be electrically written by hot electron injectionand may be electrically erased by hot hole injection or by usingultraviolet light. The following embodiments may be applied to flashbits that are programmed by any of the various means. Moreover, theembodiments infra will be explained using FN erase of a flash memoryblock but it is understood that the example embodiments are equallyapplicable to any of the methods of programming (such as hot injectionor ultraviolet light) and are equally applicable to programming anindividual flash bit, a flash memory array, a flash memory block, or aflash memory segment.

An embodiment adaptive erase method is illustrated in FIGS. 6A-6C. Theexample voltages in the following description are used for illustrativepurposes. Actual voltages may differ depending upon the capacitivecoupling and dielectric thicknesses in of the flash bit structures. Thecontrol gate erase voltage is used as the adaptive erase voltage forillustrative purposes in this embodiment, but it is understood that theisolated pwell voltage may be used as the adaptive erase voltage.Moreover, a combination of the control gate voltage and the isolatedpwell voltage may be used in the adaptive erase method.

The erase voltage versus time, at a constant −8.0 control gate voltage,is shown in FIG. 6A. The distribution of erase times for the flashblocks across a wafer is shown in FIG. 6B. A few memory blocks erase inless than 1 second but most blocks erase between 1 and 2 seconds orlonger.

As shown in Table 1, an adaptive erase voltage table may be constructed(for a given technology) between the time it takes for a flash memoryblock to erase at −8.0 V and the voltage required for that same flashmemory block to erase in less than 1 second. In this example, the timeto erase a flash memory block at −8.0 V has been divided into 1 secondincrements. (It is to be noted that different time increments would workequally well. For example, half second increments in the left handcolumn of Table 1 with correspondingly smaller voltage increments in theright hand column of Table 1 may also be used.) Once this table isconstructed for flash blocks for a given technology, it may be used toselect the correct adaptive erase voltage for flash blocks on all wafersmanufactured with that technology, as long as there is no significantchange to the baseline process flow. Therefore, once the erase time hasbeen determined for a flash block, the corresponding adaptive erasevoltage may be selected from a table (such as is shown in Table 1). Thisadaptive erase voltage may then be written into the flash block memory.The API may read this adaptive erase voltage the next time the block isto be erased and use this adaptive erase voltage to erase the memoryblock. This adaptive erase voltage may also be used in subsequent erasesof the memory block.

TABLE 1 Time in seconds to erase a Voltage required to erase the memorymemory block at −8.0 Volts block in 1 sec or less (Volts) 1 8 2 8.25 38.5 4 8.8

FIG. 6C shows the distribution of block erase times when the adaptiveerase voltages are used. The distribution is now narrow (compared to thedistribution shown in FIG. 6B), with virtually all block times erasingin less than one second. Moreover, blocks with erase times greater than3 seconds (which previously would have been scrapped due to the failureto meet the maximum programming specification of 3 seconds) may programin less than one second with the adaptive erase voltage and thereby passspecification.

Another embodiment of the adaptive erase voltage method is shown inFIGS. 7A and 7B. As shown in FIG. 7A, the erase voltage may be steppedup after each 0.5 seconds of cumulative erase time. A plot of the numberof blocks erased during each time interval is shown in FIG. 7B. In thisembodiment, the erase voltage used during each time segment becomes theadaptive erase voltage that is written into each flash memory block thatverified erase at that adaptive erase voltage. This adaptive erasevoltage may then be used to erase that block during future erases. Fourdifferent adaptive erase voltage levels and time segments are used toillustrate this embodiment, but it is understood that a different numberof time segments and adaptive erase voltages may be used. While twodifferent methods of determining the adaptive erase voltages arepresented supra, it is understood that other methods may be used todetermine adaptive erase voltages.

As the number of write and read cycles accumulates on a flash memoryblock, the time needed to erase and time needed to write to the flashmemory may increase. A well know dielectric wear out phenomena is calledcharge to dielectric breakdown (“QBD”); it is defined as the amount ofcharge that can flow through a dielectric film before it breaks down.Each time a flash bit writes and erases, a current or charge flowsthrough the gate dielectric. On occasion, this current flow causes abond to break in the dielectric, thereby forming a defect which may trapan electron. These trapped electrons may accumulate over time, causingthe Vt of the transistor to increase and resulting in a longer time towrite or to erase that flash bit.

FIGS. 8 and 9A-9C illustrate a method for resetting the adaptive erasevoltage throughout the lifetime of a flash circuit. This method mayprolong the lifetime of the flash integrated circuit by keeping theflash memory block write and block erase times within specificationthroughout the targeted lifetime of the flash integrated circuit. The FNerase operation will be used to illustrate this embodiment, but it isunderstood that the write operation also benefits from this method. Theillustrated embodiment uses block erase 108, but it is also understoodthat it could be a flash memory erase 106 a flash sector erase 110, oran erase of some other portion of the flash memory.

A flow diagram 8000 of this embodiment is shown in FIG. 8. In thebeginning step 8002, the API 104 receives a memory access request fromthe CPU 102. The API 104 sends the proper signals to the specifiedmemory location 106 to erase and then rewrite new data into the memoryblock 108 using an initial programming voltage on the control gate. Eachtime a flash block Goes through an erase 8004/verify 8006 and/or write8008/verify 8010 cycle, the API program checks 8012 the index counter8018 to see if that block has then been reprogrammed (erased andrewritten) a predetermined number of times 500 times is used in thisexample). If not, then the counter 8018 is incremented and the API 104waits for the next erase/write request 8002 from the CPU 102. If,however, the block has been reprogrammed 500 times, step 8020 checks tosee if the erase programming time 8016 has lengthened into one of thelonger erase time bins, such as is illustrated in Table 1. If it haslengthened, then a new adaptive erase voltage is selected and writteninto the flash block memory 8022. This new adaptive erase voltage isthen used during subsequent erase/write cycles 8004-8010. In addition,the adaptive erase voltage may be updated after each additional 500erase/write cycles, if needed. In step 8014, the write/erase cyclecounter is reset and the API 104 waits for the next erase/write request8002 from the CPU 102. In the example embodiment, the applicationprogrammer interface (API) 104 contains the program that performs thestep sequences shown in FIG. 8. The times, voltages, and number oferase/write cycles used for the method of FIG. 8 are for illustrativepurposes only. The actual times, voltages, and number of erase/writecycles may change, depending upon process technology and circuit designdetails.

FIGS. 9A through 9C shows a distribution of block erase times using theadaptive erase voltage method described in FIG. 8. FIG. 9A shows thedistribution of block erase times after one erase/write cycle. FIG. 9Bshows the distribution of block erase times after 500 erase/writecycles. The erase time of a significant number of the memory blocks hasincreased to over 1 second. FIG. 9C shows the distribution of blockerase times after 501 erase/cycles and after updated adaptive erasevoltages are applied, in accordance with the method of FIG. 8.

FIG. 10 is a flow diagram 1000 of a write operation and an eraseoperation in a flash memory. Again for illustration, 500 erase/writecycles are completed (a different cut-off number could have beenselected) before checking whether the erase or write program times havelengthened to the extent that a new adaptive erase voltage or adaptivewrite voltage is required. Because all of the flash bits in a memorysector 110 or memory block 108 are simultaneously erased, only oneadaptive erase voltage is typically saved for that sector or block.Alternatively, because words or rows are typically written individually,several adaptive write voltages may be saved if there are severalslow-to-write words or rows in a memory sector or memory block. Forexample, individual adaptive write voltages may be saved for each memorysector in a memory block or for several words or rows in a memorysector. Alternatively, one adaptive write voltage may be saved formultiple slow rows in a memory sector or memory block.

An example embodiment using both adaptive write voltage and adaptiveerase voltages is illustrated in FIG. 10. The operation starts in step1002 when the CPU 102 sends an erase/write request to the API 104 thatin turn sends the appropriate signals to the flash memory 106 to performthe requested task. The requested memory sector 110 or memory block 108is erased in step 1004 and the erase is verified in step 1006. If theerase is not verified then the program may return to step 1004 for anadditional erase cycle. The erase time for the last erase/write cycle isstored in step 1022. After a flash bit has undergone a number oferase/write cycles, charge may become trapped in the tunnel oxidecausing the erase time to lengthen.

After the erase is verified in step 1006, the data is written into thememory block in step 1008. The data may be written into the flash memoryeither one word or one memory row at a time. The write time may bestored 1010 by word or by memory row for each word or memory row in thememory block. If the write operation of a word or memory row is notverified in step 1012 then the API program may return to step 1008 torepeat the write operation until it is successfully verified in step1012.

After the entire memory block is successfully erased and written, theindex counter 1024 may be checked in step 1014 to determine if it hasbeen written 500 times since the last adaptive programming voltageupdate. If not, the index counter 1024 is incremented and the API 104waits for the next erase/write request. If, however, 500 write cycleshave been performed since the last adaptive programming voltage update,the erase time from step 1022 is checked in step 1016 to see if theerase time has lengthened to the point where a new adaptive erasevoltage is required. If a new adaptive erase voltage for the memoryblock is needed, then the new adaptive erase voltage is selected andwritten into flash memory in step 1018 to be used in subsequent erasecycles. The new adaptive erase voltage may be selected from a tablesimilar to Table 1 or calculated using an algorithm that has beencalibrated using adaptive erase data.

The write time 1010 for each word or memory row may be checked 1020 todetermine if any have lengthened to the point where a new adaptive writevoltage is required. If one or more have, new adaptive write voltagesare selected and written into memory in step 1028 to be used to writethose words or memory rows in subsequent write cycles. The new adaptivewrite voltage may be selected from a table similar to Table 1 that isprepared for write adaptive voltages or may be calculated using analgorithm that has been calibrated using adaptive write voltage data.The counter is then reset to zero in step 1026 to begin the next set of500 erase/write cycles.

The number of erase/write cycles between each adaptive programmingvoltage update, block erase, and word or memory row write, that arediscussed supra are for illustrative purposes only. Other numbers oferase/write cycles, other numbers of erased bits per cycle, and othernumbers of written bits or bytes per cycle may also be used. In theembodiment described in FIG. 10, the erase time check 1016 and update1018 steps are performed before the write time check 1020 and update1028 steps are performed; but steps 1020 and 1028 may be performedbefore steps 1016 and 1018 if desired.

Although an NMOS flash memory is used to illustrate the aboveembodiments, a PMOS flash memory such as is described in FIGS. 11A and11B may instead be used. A PMOS flash bit 1100 may be formed in an nwell1102 that is formed in a p-type substrate 1101. During an eraseoperation, a high voltage 1114 (i.e. about 17V) may be applied to thecontrol gate 1112 which is capacitively coupled to the floating gate1108 through the interpoly dielectric 1110. The source 1104 and drain1118 may be floated during the erase operation. The high voltage 1114 onthe control gate 1112 raises the potential on the floating gate 1108;encouraging electrons to tunnel through the gate dielectric 1106 andcausing the voltage on the floating gate 1108 to become approximatelyneutral. During a read operation the voltage 1114 on the control gate1112 of the PMOS flash bit is changed from Vdd to ground, causing thePMOS flash transistor to turn on, thereby indicating an erased state.

As shown in FIG. 11B, the PMOS flash bit 1200 may be programmed byapplying a negative voltage 1214 (i.e. about −8.5V) to the control gate1212 and a positive voltage 1216 (i.e. about +8.5V) to the nwell 1202.The source 1204 and drain 1218 may be floated during the programoperation. The negative voltage 1214 on the control gate 1212, incombination with the positive voltage 1216 on the nwell 1202, causeselectrons to tunnel off the floating gate 1208 and into the nwell 1202through the gate dielectric 1206. This leaves a residual positivevoltage on the floating gate 1208. During a read operation, the voltage1214 on the control gate 1212 of the PMOS flash bit 1200 is changed fromVdd to zero. The residual positive charge on the floating gate 1208prevents the PMOS flash transistor from turning on, thereby indicating aprogrammed state.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only and notlimitation. Numerous changes to the disclosed embodiments can be made inaccordance with the disclosure herein without departing from the spiritor scope of the embodiments. Thus, the breadth and scope of theembodiments should not be limited by any of the above-describedembodiments. Rather, the scope of the embodiments should be defined inaccordance with the following claims and their equivalents.

1. A method for programming a flash memory comprising: determining atime to program a portion of said flash memory at a programming voltage;determining an adaptive programming voltage based upon said time toprogram said portion of said flash memory at said programming voltage;and using said adaptive programming voltage for future programming ofsaid portion of said flash memory.
 2. The method of claim 1 wherein saidprogramming is an erase operation.
 3. The method of claim 1 wherein saidprogramming is a write operation.
 4. The method of claim 1 where in saidprogramming is an erase operation plus a write operation.
 5. The methodof claim 1 wherein said adaptive programming voltage is a control gatevoltage.
 6. The method of claim 1 wherein said adaptive programmingvoltage is a well voltage.
 7. The method of claim 1 wherein said portionof said flash memory is a memory block, a memory sector, or all bits insaid flash memory.
 8. The method of claim 1 where said adaptiveprogramming voltage is a control gate voltage plus a well voltage.
 9. Amethod of programming a flash circuit, comprising: indexing a counterafter each erase/write cycle is performed on a portion of a flash memoryin said flash circuit; checking a programming time after said counterreaches a predetermined number of erase/write cycles; when said counterreaches said predetermined number of erase/write cycles and saidprogramming time exceeds a programming time specification, selecting anew adaptive programming voltage, then writing said new adaptiveprogramming voltage into said flash memory, and using said new adaptiveprogramming voltage for future programming of said portion of said flashmemory; and resetting said counter after reaching said predeterminednumber of erase/write cycles.
 10. The method of claim 9 wherein saidprogramming is to erase said flash memory in said flash circuit.
 11. Themethod of claim 9 wherein said programming is to write to said flashmemory in said flash circuit.
 12. The method of claim 9 wherein saidprogramming is an erase plus a write to said flash memory in said flashcircuit.
 13. The method of claim 9 wherein said adaptive programmingvoltage is a control gate voltage.
 14. The method of claim 9 whereinsaid adaptive programming voltage is a well voltage.
 15. The method ofclaim 9 wherein said portion of said flash memory is a memory block, amemory sector, or all bits in said flash memory.
 16. The method of claim9 where said adaptive programming voltage is a control gate voltage plusa well voltage.